A recent technical paper from The University of Edinburgh introduces “EEsizer,” an innovative AI agent utilizing Large Language Models (LLMs) for the automated sizing of Analog and Mixed-Signal (AMS) circuits. The design of AMS integrated circuits typically requires extensive manual effort, particularly during the transistor sizing phase. While existing Machine Learning techniques in Electronic Design Automation (EDA) have reduced complexity, they still rely on repetitive iterations and knowledge gaps. EEsizer bridges this gap by integrating LLMs with circuit simulators, enabling a closed-loop sizing process independently. The research benchmarks 8 LLMs on basic circuits, selecting three high-performing models to optimize a 20-transistor CMOS operational amplifier. Demonstrated success includes achieving user-defined targets in advanced technology nodes (90 nm), showcasing the agent’s capability and robustness. The paper validates design resilience through variation analysis of transistor dimensions and voltages. Explore the full study for advanced insights in EDA.
Find the technical paper here.
